Memory devices including dielectric thin film and method of manufacturing the same

ABSTRACT

A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication Nos. 2005-117717, filed Dec. 5, 2005, and 2006-44063, filedMay 17, 2006, the disclosures of which are incorporated herein byreference in their entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a memory device and a method ofmanufacturing the same, and more particularly, to a memory deviceincluding a dielectric thin film having a plurality of dielectric layersand a method of manufacturing the same.

2. Discussion of Related Art

Non-volatile memory devices are information storage devices typicallyemployed in cellular phones, digital cameras, MP3 players, and the like.The use of non-volatile memory devices in these and various otherdevices is extremely widespread, and demand for mass storage of data isrecently increasing. In addition, non-volatile memory devices arecommonly used in mobile devices which require that they operate at lowpower.

Flash memory devices, which control accumulation of charge on a floatinggate to store data, are the most widespread type of non-volatile memorydevice. However, since flash memory devices have a structure in whichcharge is accumulated on a floating gate in the presence of a strongelectric field, the device structure becomes relatively complicated anddifficult to densely integrate.

To overcome this problem, the Ovonic Unified Memory (OUM), anelectrically erasable non-volatile memory device, was proposed. The OUMuses a difference in electrical conductivity between a crystalline stateand a non-crystalline state of a memory layer, and has a simplestructure compared to a flash memory so that it can be highly integratedin theory. However, heat is required for a phase change from thecrystalline state to the noncrystalline state of the memory layer in theOUM, which requires a current of about 1 mA per cell. Consequently,thick interconnections are required, which again makes it difficult toobtain high integration.

To cope with this problem, non-volatile memory devices allowing anelectrical resistance to change without a phase change are disclosed inKorean Patent Publication No. 2004-0049290 and Japanese Laid-Open PatentPublication No. 2004-185756. The non-volatile memory devices disclosedin these documents are based on the principle of forming an oxide havinga perovskite structure containing Mn and applying a voltage pulse tochange electrical resistance.

However, materials such as Mn oxide layers disclosed in the citeddocuments (e.g., PrCaMnO, LaCaMnO, LaCaPbMnO, or the like) require ahigh process temperature and have complicated structures. Consequently,manufactured structures may easily deviate from what is necessary forthe memory device to function properly. Accordingly, such devices aredifficult to manufacture.

SUMMARY OF THE INVENTION

The present invention is directed to a method of a manufacturing memorydevice, capable of manufacturing a non-volatile memory device using asimple manufacturing process. The present invention is also directed toa memory device, which can be highly integrated by a simplemanufacturing process.

One aspect of the present invention provides a memory device,comprising: a bottom electrode; at least one dielectric thin filmdisposed on the bottom electrode and having a plurality of dielectriclayers with different charge trap densities from each other; and an topelectrode disposed on the dielectric thin film.

Preferably, different space-charge limit currents may flow in thedielectric thin film according to the charge trap densities. Thespace-charge limit current may be controlled according to an impurityadded to the dielectric layer. The dielectric layer may use a dielectricformed of TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, PdO, or a materialin which at least one of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Hf, Nb,Ta, Pd, and La group elements is added to TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅,Ta₂O₅, NiO, or PdO, as an impurity; a dielectric of ABO₃ type; or adielectric consisting of a material having a perovskite structure exceptthe ABO₃ type, and impurities added to the material. The charge trapdensity may range from 10¹⁷/cm³ to 10²¹/cm³. The dielectric thin filmmay be formed to a thickness of 3 nm to 100 nm. The dielectric constantof the dielectric layer may range from 3 to 1000.

Another aspect of the present invention provides a method ofmanufacturing a memory device, comprising the steps of: forming a bottomelectrode; forming at least one dielectric thin film having a pluralityof dielectric layers with different charge trap densities from eachother on the bottom electrode; and forming an top electrode on thedielectric thin film.

Preferably, the step of forming the dielectric thin film may comprisethe steps of: forming a lower dielectric layer on the bottom electrode;and forming an upper dielectric layer using a dielectric equal to ordifferent from the lower dielectric layer on the lower dielectric layer.The step of forming the dielectric thin film may comprise the step offorming an intermediate dielectric layer using a dielectric equal to atleast one of the lower and upper dielectric layers or a dielectricdifferent from the lower and upper dielectric layers, between the lowerdielectric layer formed on the bottom electrode and the upper dielectriclayer formed on the lower dielectric layer.

The intermediate dielectric layer may act as a barrier which preventstraps included in the lower and upper dielectric layers from moving.When the lower dielectric layer, the intermediate dielectric layer, andthe upper dielectric layer are formed of the same dielectric, depositionconditions of the respective dielectric layers may be made to bedifferent from each other. The deposition condition may be at least oneof a deposition temperature, a deposition time, a deposition rate and adeposition method. The dielectric thin film may have a thickness of 3 nmto 100 nm. The dielectric layer may be formed of a dielectric having adielectric constant in a range of 3 to 1000. The dielectric layer mayuse a dielectric formed of TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO,PdO, or a material in which at least one of Ti, V, Cr, Mn, Fe, Co, Ni,Cu, Zn, Zr, Hf, Nb, Ta, Pd, and La group elements is added to TiO₂,ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, or PdO, as an impurity; adielectric of ABO₃ type; or a dielectric consisting of a material havinga perovskite structure except the ABO₃ type, and impurities added to thematerial.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail preferred embodiments thereof with reference to theattached drawings in which:

FIG. 1 is a schematic side cross-sectional view of a memory devicehaving a dielectric thin film in accordance with an embodiment of thepresent invention;

FIG. 2 is a schematic side cross-sectional view of a memory devicehaving a dielectric thin film in accordance with another embodiment ofthe present invention;

FIG. 3 is a schematic side cross-sectional view of a memory devicehaving a dielectric thin film in accordance with yet another embodimentof the present invention;

FIG. 4 is a graph of log I versus V of a memory device in accordancewith an embodiment of the present invention.

FIG. 5 is a logarithmic graph of current I versus voltage V when anegative voltage is applied to a memory device in accordance with anembodiment of the present invention;

FIG. 6 is a logarithmic graph of current I versus voltage V when apositive voltage is applied to a memory device in accordance with anembodiment of the present invention; and

FIG. 7 is a graph showing switching characteristics of a memory deviceof which currents are measured while a negative voltage and a positivenegative are repeatedly applied to the memory device in accordance withan embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, memory devices according to exemplary embodiments of thepresent invention will be described in detail with reference toaccompanying drawings.

FIG. 1 is a schematic side cross-sectional view of a memory devicehaving a dielectric thin film in accordance with an embodiment of thepresent invention. Referring to FIG. 1, the memory device 100 accordingto an embodiment of the present invention includes a substrate 110, abottom electrode 120 disposed on the substrate 110, a dielectric thinfilm 130 disposed on the bottom electrode 120, and an top electrode 125disposed thereon. The dielectric thin film 130 shown in FIG. 1 includesa lower dielectric layer 130 a and an upper dielectric layer 130 b.

The dielectric thin film 130 having a plurality of dielectric layers 130a and 130 b using the same dielectric is shown in FIG. 1. As shown inFIG. 1, when the same dielectric is used, the dielectric layers havingdifferent trap charge densities can be formed by making depositionconditions (e.g., deposition temperature, deposition time, depositionrate, deposition method, or the like) different from each other for eachdielectric layer in consideration of intrinsic defects generated due tolack or excess of specific atoms among atoms constituting a material orextrinsic defects generated due to doped impurities.

FIG. 2 is a schematic side cross-sectional view of a memory devicehaving a dielectric thin film in accordance with another embodiment ofthe present invention. Referring to FIG. 2, a memory device 200according to another embodiment of the present invention includes asubstrate 110, a bottom electrode 120 disposed on the substrate 110, adielectric thin film 230 disposed on the bottom electrode 120, and antop electrode 125 disposed thereon. The dielectric thin film 230 shownin FIG. 2 includes a lower dielectric layer 231 and an upper dielectriclayer 232.

The dielectric thin film 230 having a plurality of dielectric layers 231and 232 using different dielectrics is shown in FIG. 2. When thedifferent dielectrics are used, the same deposition condition anddifferent deposition conditions can be used, and different dielectriclayers can be formed even when the same deposition condition is used.

Referring to FIGS. 1 and 2, the memory devices 100 and 200 of thepresent invention have a thin film type condensor structure, which hasthe dielectric thin films 130 and 230 composed of a plurality of stackeddielectric layers 130 a and 130 b, and 231 and 232 and having apredetermined dielectric constant between the bottom electrode 120 andthe top electrode 125. The dielectric layers 130 a and 130 b, and 231and 232 use a dielectric having a dielectric constant of 3 to 1000, andthe dielectric thin films 130 and 230 are preferably formed to arelatively thin thickness so as to form a relatively large electricfield with respect to a voltage applied to the memory device. In thepresent embodiment, the dielectric thin films 130 and 230 are formed toa thickness of 3 nm to 100 nm, and may be formed of organic materials aswell as inorganic materials.

Electrical characteristics of the lower dielectric layers 130 a and 231constituting the dielectric thin films 130 and 230 are different fromthose of the upper dielectric layers 130 b and 232 constituting thedielectric thin films 130 and 230 according to a direction of an appliedvoltage. For example, the lower dielectric layers 130 a and 231 and theupper dielectric layer 130 b and 232 may be manufactured so as to have acharacteristic that a trap-unfilled space charge limited current (SCLC)flows in a state that charges are discharged from a trap present withinthe dielectric thin film and a characteristic that a trap-filled SCLCflows in a state that charges are filled within the trap, according tothe direction of the applied voltage. In addition, the dielectric thinfilms 130 and 230 may be manufactured to have a characteristic thattraps are hardly found in the dielectric thin films 130 and 230, acharacteristic that there are many traps for capturing electrons, acharacteristic that there are many traps for capturing holes, or aproper combination thereof.

When the charge trap density per unit volume of each dielectric layer isnot less than a predetermined level as described above, currents flowthrough the dielectric thin films 130 and 230 due to the SCLC which isan electrical transport characteristic. The charge trap density per unitvolume ranges from 10¹⁷/cm³ to 10²¹/cm³ in the present embodiment.

Meanwhile, impurity ions are doped on the dielectric layer in order tocontrol the SCLC. The dielectric layer is composed of TiO₂, ZrO₂, HfO₂,V₂O₅, Nb₂O₅, Ta₂O₅, NiO, PdO, or a material in which at least one of Ti,V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Hf, Nb, Ta, Pd, and La group elementsis added to TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, or PdO, as animpurity. In addition, in order to form the dielectric layer, adielectric of ABO₃ type (e.g., (Group 1 element)(Group 5 element)O₃ or(Group 2 element)(Group 4 element)O₃) may be used. In this case, thedielectrics of (Group 1 element)(Group 5 element)O₃ include LiNbO₃,LiTaO₃, NaNbO₃, . . . (Li,Na)(Nb,Ta)O₃, (Li,Na,K)(Nb,Ta)O₃, and soforth, and the dielectrics of (Group 2 element)(Group 4 element)O₃include CaTiO₃, SrTiO₃, BaTiO₃, PbTiO₃, . . . , Pb(Zr,Ti)O₃, . . .(Ca,Sr,Ba,Pb)(Ti,Zr)O₃, YMnO₃, LaMnO₃, and so forth. In anotherembodiment, the dielectric layer may use a dielectric consisting of amaterial (e.g., Bi₄Ta₃O₁₂, . . . (Sr,Ba)Nb₂O₆ or the like) having aperovskite structure except the ABO₃ type, and impurities added to thematerial. A dielectric constant of the dielectric layer is selected in arange of 3 to 1000, and the dielectric of ABO₃ type is a ferroelectrichaving a relatively high dielectric constant compared to other materialsand has a dielectric constant of about 100 to about 1000, and the restof the dielectrics have a dielectric constant of 3 to several hundreds.

FIG. 3 is a schematic side cross-sectional view of a memory devicehaving a dielectric thin film in accordance with yet another embodimentof the present invention. Referring to FIG. 3, a memory device 300includes a substrate 110, a bottom electrode 120 disposed on thesubstrate 110, a dielectric thin film 330 disposed on the bottomelectrode 120, and an top electrode 125 disposed on the dielectric thinfilm 330. The dielectric thin film 330 shown in FIG. 3 includes a lowerdielectric layer 331, an intermediate dielectric layer 332 disposed onthe lower dielectric layer 331, and an upper dielectric layer 333disposed on the intermediate dielectric layer 332.

The memory device 300 according to the present embodiment also has athin film type condensor structure, which includes a dielectric thinfilm 330 composed of a plurality of dielectric layers 331, 332, and 333having a predetermined dielectric constant between the bottom electrode120 and the top electrode 125 in the same way as the memory devices 100and 200 shown in FIGS. 1 and 2. The dielectric layers 331, 332, and 333are formed of a dielectric having a dielectric constant of 3 to 1000,and may be formed of the same material as that described with referenceto FIGS. 1 and 2. The dielectric thin film 330 is preferably formed to arelatively thin thickness so as to form a relatively large electricfield with respect to a voltage applied to the memory device 300, andthe dielectric thin film 330 can be formed to a thickness of 3 nm to 100nm in the present embodiment. For simplicity of description, electricalcharacteristics of the lower dielectric layer 331 and the upperdielectric layer 333 and description of the same constitutional elementsas those of FIGS. 1 and 2 can be referred to the description of FIGS. 1and 2.

In addition, the intermediate dielectric layer 332 formed on the lowerdielectric layer 331 acts as a barrier for preventing traps included inthe lower dielectric layer 331 and the upper dielectric layer 333 frommoving to another dielectric layer. Consequently, the intermediatedielectric layer 332 prevents the traps from moving to the dielectriclayer having a different trap charge density, so that the memory effectis enhanced. The intermediate dielectric layer 332 of FIG. 3 may beformed of a dielectric material different from each of the upperdielectric layer 333 and the lower dielectric layer 331, or may beformed of the same dielectric material as one of the upper dielectriclayer 333 and the lower dielectric layer 331. When the same dielectricmaterial is used, deposition can be carried out using differentdeposition conditions (e.g., deposition temperature, deposition time,deposition rate, deposition method, or the like) per each dielectriclayer to form dielectric layers having different trap charge densitiesfrom each other. A detailed description of the charge trap density andthe material for forming the dielectric layer will also be referred tothe descriptions of FIGS. 1 and 2.

As described above, in the memory devices 100, 200, 300 manufacturedincluding the bottom electrode 120, the dielectric thin films 130, 230,and 330, and the top electrode 125, an electrical conductivity ischanged according to a voltage applied between the bottom electrode 120and the top electrode 125. The state of the electrical conductivity ofthe dielectric layer is kept even when the voltage is not appliedthereto. To detail this, a high conductivity is kept when the electricalconductivity of the dielectric layer is in a high conductivity state,and a low conductivity is kept when the electrical conductivity of thedielectric layer is in a low conductivity state.

The dielectric thin films 130, 230, and 330 will now be described indetail. In general, current hardly flows through a dielectric unlikemetal and semiconductor. However, a strong electric field is generatedwhen a voltage is applied to very thin dielectric thin films 130, 230,and 330. In this case, an ohmic current that the current is inproportion to the voltage (I∝V) flows when a low voltage is applied tothe dielectric thin films 130, 230, and 330, and an SCLC that thecurrent is in proportion to the square of the voltage flows when a highvoltage is applied to the dielectric thin films. When a charge trap dueto an impurity is present in the dielectric thin film, the SCLC isdetermined by Equation 1 below.

$\begin{matrix}{J = {\frac{9}{8}{ɛ\mu\theta}\frac{V^{2}}{d^{3}}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

wherein, J denotes a current density, ∈ denotes a dielectric constant, μdenotes a charge mobility, V denotes a voltage, and d denotes athickness. 74 denotes a ratio between a free charge density (n) and atrapped charge density (n_(t)), which is given as Equation 2 below.

$\begin{matrix}{\theta = \frac{n}{n_{t}}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

VT (threshold voltage, see FIG. 5) denotes a trap-filled limit voltage(V_(TFL)), and complies with Equation 3 below.

$\begin{matrix}{V_{TFL} = \frac{{eN}_{t}d^{2}}{2_{ɛ}}} & {{Equation}\mspace{14mu} 3}\end{matrix}$

wherein N_(t) denotes a trap density.

According to Equation 3, in case of memory device using an SCLC, thethreshold voltage and current flowing through the memory device can becontrolled by adjusting a dielectric constant of the dielectric layer, atrap density, a thickness of the dielectric layer, or the like. Thecharge trap captures only one kind of charge of an electron and a hole,and when such traps are distributed in an irregular way at upper andlower sides within the thin film, the current flowing in the thin filmcan be divided into a trap-filled SCLC and a trap-unfilled SCLCaccording to a direction of a voltage that is applied from the exterior.Conductivities of the two states are different from each other, and canbe switched to different states from each other at the threshold voltage(V_(T), V*_(T)) or more. Such a phenomenon can be employed tomanufacture a variable resistance type memory device. In this case,performance of the non-volatile memory can be controlled according tothe kind of the dielectric and the trap characteristics.

When several dielectric layers having different characteristics aremanufactured in a multilayered thin film structure in accordance withthe present embodiment, effective voltages (V₁, V₂, . . . ) applied tothe respective layers can be controlled by Equation 4 below, andtherefore, the non-volatile memory device having good characteristicscan be manufactured.

$\begin{matrix}{{Q = {CV}},{V = {V_{1} + V_{2} + \ldots}}\mspace{14mu},{\frac{1}{C} = {\frac{1}{C_{1}} + \frac{1}{C_{2}} + \ldots}}\mspace{14mu},{\frac{C}{A} = {\frac{ɛ_{0}ɛ_{1}}{d_{1}} = \frac{ɛ_{0}ɛ_{2}}{d_{2}}}}} & {{Equation}\mspace{14mu} 4}\end{matrix}$

wherein Q denotes the amount of charge, V denotes a voltage, C denotes acapacitance, A denotes a current, d denotes a thickness, and ∈ denotes adielectric constant. Accordingly, the whole characteristics of thedevice can be changed when each thickness is changed.

As described above, when at least two dielectric thin films are stackedto manufacture the memory device, degradation of the characteristics ofthe memory device can be controlled. When a plurality of dielectric thinfilms are used to manufacture the memory device, the upper dielectriclayer constituting the lower dielectric thin film and the lowerdielectric layer constituting the upper dielectric thin film can becontrolled according to Equation 4, i.e., the intensity of an electricfield applied to each layer can be determined according to the thicknessand dielectric constant of each dielectric layer.

FIG. 4 is a graph of log I versus V of a memory device in accordancewith an embodiment of the present invention. FIG. 4 is a graph showingcurrent-voltage characteristics of the memory device, and its verticalaxis denotes log I (current), and its horizontal axis denotes a voltage.Referring to the graph, after a negative voltage is applied, i.e., when3V is changed to −3V (3V->−3V), the trap-filled SCLC flows to decreaseresistance, however, after a positive is applied, that is, when −3V ischanged to 3V (−3V->3V), the trap-unfilled SCLC flows to increaseresistance.

FIG. 5 is a logarithmic graph of current I versus voltage V when anegative voltage is applied to a memory device in accordance with anembodiment of the present invention. When a voltage applied to thememory device goes from 0V to −3V and from −3V to 0V, an ohmic currenthaving a slope of almost 1 flows at a low voltage. However, the slopeslowly increases at higher voltages and rapidly increases when itreaches the threshold voltage (VT). At this point the state changes fromthe trap-unfilled SCLC to the trap-filled SCLC. Afterwards, a lowresistance is kept at a negative voltage of magnitude smaller than V_(T)because of the trap-filled SCLC.

FIG. 6 is a logarithmic graph of current I versus voltage V when apositive voltage is applied to a memory device in accordance with anembodiment of the present invention. When the voltage applied to thememory device increases from 0V to 3V, an ohmic current having a slopeof 1 flows at a low voltage, and the state changes to the trap-filledSCLC state at a high voltage. And, the voltage decreases with a lesserslope at the threshold voltage (V_(T)*) so that the state changes fromthe trap-filled SCLC to the trap-unfilled SCLC. Afterwards, a statehaving a high resistance is kept due to the trap-unfilled SCLC at apositive voltage and a negative voltage of lesser magnitude than thethreshold voltage.

When characteristics of the memory device of FIGS. 4 to 6 are undertest, a limit current of 1 mA is applied to measurement equipment formeasuring the characteristics of the memory device to prevent the memorydevice from being damaged. Therefore, a voltage of about −2.7V to about2.9V is actually applied to the measurement equipment even when ±3V isapplied thereto, so that the memory device itself can be prevented frombeing damaged.

FIG. 7 is a graph showing switching characteristics of a memory deviceof which currents are measured while a negative voltage and a positivenegative are repeatedly applied to the memory device in accordance withan embodiment of the present invention. Referring to FIG. 7 representingthe switching characteristics of the non-volatile memory device, itshorizontal axis denotes a time, and its lower vertical axis denotes avoltage and its upper vertical axis denotes a current. A currentmeasured at −1V after a pulse of −3V is applied to the memory device isabout −0.7 mA, and a current measured at −1V after a pulse of +3V isapplied to the memory device is about −0.2 mA. Consequently, the memorydevice has a switching characteristic that the current is changed (in arange of −0.7 mA to −0.2 mA) according to the change in applied voltage.

According to the dielectric thin film having the above-described memorycharacteristics, that is, when dielectric materials are stacked in aplurality of layers, it can be seen that the memory effect can be foundbecause of the (state) change in SCLC. For example, in a case of a TIO₂layer formed to a thickness of 10 nm by a Metal Organic Chemical VaporDeposition (MOCVD) method, an Atomic Layer Deposition (ALD) method, asputtering method, a spin coating method, or the like, when a highelectric field enough to cause the memory effect is applied thereto,electrical resistance changes according to the voltage pulse, so thatthe memory effect was significantly enhanced in the structures shown inFIGS. 1 to 3. In addition, a memory device having a dielectric thin filmformed of various dielectric materials such as ZrO₂ and HfO₂ and adielectric of a perovskite structure that does not contain Mn can alsoenhance the memory effect, and it can also be observed that the memoryeffect is enhanced according to the material added to the dielectriceven when the memory effect is insignificant. For example, it can beseen that the memory effect is enhanced even when the dielectric layeruses a dielectric formed of TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO,PdO, or a material in which at least one of Ti, V, Cr, Mn, Fe, Co, Ni,Cu, Zn, Zr, Hf, Nb, Ta, Pd, and La group elements is added to TiO₂,ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, or PdO, as an impurity; adielectric of ABO₃ type; or a dielectric consisting of a material havinga perovskite structure except the ABO₃ type, and impurities added to thematerial.

As described above, a memory device in accordance with the presentinvention is manufactured using a dielectric thin film having astructure where a plurality of dielectric layers are stacked, to have asimple structure compared to the conventional memory device, therebyenhancing productivity and integration density.

In addition, a memory device where dielectric layers are stacked using atrap-controlled space-charge-limited current is manufactured, so thatcurrent gain in on/off states can be enhanced compared to theconventional memory device using one dielectric layer.

While the invention has been shown and described with reference tocertain exemplary embodiments thereof, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims.

1. A method of manufacturing a memory device, comprising the steps of:forming a bottom electrode; forming at least one dielectric thin filmhaving a plurality of dielectric layers with different charge trapdensities from each other on the bottom electrode; and forming an topelectrode on the dielectric thin film.
 2. The method of claim 1, whereinthe step of forming the dielectric thin film comprises the steps of:forming a lower dielectric layer on the bottom electrode; and forming anupper dielectric layer using a dielectric equal to or different from thelower dielectric layer on the lower dielectric layer.
 3. The method ofclaim 1, wherein the step of forming the dielectric thin film comprisesthe step of forming an intermediate dielectric layer using a dielectricequal to at least one of the lower and upper dielectric layers or adielectric different from the lower and upper dielectric layers, betweenthe lower dielectric layer formed on the bottom electrode and the upperdielectric layer formed on the lower dielectric layer.
 4. The method ofclaim 3, wherein the intermediate dielectric layer acts as a barrierwhich prevents traps included in the lower and upper dielectric layersfrom moving.
 5. The method of claim 2, wherein when the lower dielectriclayer, the intermediate dielectric layer, and the upper dielectric layerare formed of the same dielectric, deposition conditions of therespective dielectric layers are different from each other.
 6. Themethod of claim 5, wherein the deposition condition is at least one of adeposition temperature, a deposition time, a deposition rate and adeposition method.
 7. The method of claim 1, wherein the dielectric thinfilm has a thickness of 3 nm to 100 nm.
 8. The method of claim 1,wherein the dielectric layer is formed of a dielectric having adielectric constant ranging from 3 to
 1000. 9. The method of claim 1,wherein the dielectric layer is composed of: a dielectric formed ofTiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, PdO, or a material in whichat least one of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Hf, Nb, Ta, Pd,and La group elements is added to TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅,NiO, or PdO, as an impurity; a dielectric of ABO₃ type; or a dielectricconsisting of a material having a perovskite structure, except the ABO₃type, and impurities added to the material.